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SA8803 LIGHT EMITTING DIODE DRIVER
FEATURES n Drives 24 LED's under control of Serial n 11 Bit Information word controls up to 192 LED's (using eight SA8803s) Interface n Light Emitting Diode intensity n Readback of LED status programmable using a single resistor n Requires a local clock of 8 times the data rate n Automatic lamp test facility on reset (MRST) n Constant current from power supply option n Minimal external components n LED intensity constant, regardless of number of LED's illuminated PIN CONNECTIONS DESCRIPTION The block Diagram of the SA8803 is shown in Fig. 1. A control word is clocked into the device via the DATA pin with a local clock provided to pin CLK. The control word comprises a 3-bit chip address, a 5-bit LED address and a Status (on/off) bit. Provided that the Chip Adress matches the setting on pins AD0..AD2 then the LED State Register is TEST addressed and the state of the selected LED LED 1 LED 2 LED 24 is set according to the Status bit in the Control LED 3 LED 23 word. LED 22 LED 4 V EE The LEDs are driven by banks of Constant V EE LED 21 Current Sources in which the value of the LED 5 SA8803 LED 20 current in all six banks is set by a single LED 6 LED 7 LED 19 external resistor connected between pin V V DD DD INTENS and VEE. The total current drained LED 8 LED 18 by the device and the LEDs may be fixed at LED 9 LED 17 six times the LED current by connecting pin CC to GND. The status of all LEDs can be verified at any DR-00593 time by pulling the TEST pin low. When tis happens the contents of the LED Status Register are clocked out of the SA8803 on the pin DOUT. An additional test feature is that al LEDs are illuminated for a short period after power up to simplify system testing.
DOUT DATA V DD AD 0 MRST
42
GND
AD 2
AD 1
CLK
41
6
5
4
3
2
1
44
43
7 8 9
N.C.
40 28
CC
39 38 37 36 35 34 33 32
10 11 12 13 14
15 16 17
31 30 29
18
19
20
21
22
23
24
25
26
27
INTENS
LED 14
LED 15 V EE
LED 11
LED 12
LED 13
LED 10 V EE
LED 16
V DD
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PDS039-SA8803-001
REV. C
07-03-96
SA8803 FIGURE 1: BLOCK DIAGRAM
INTENS CC DATA START BIT DETECTION SIN CLK RESET START BIT
11 - BIT SHIFT REGISTER
3-BIT STOP CHIP BIT ADDRESS
COMPARATOR CLK CLOCK SYNC S CLK
LED SELECTION BUS
LED1 24-BIT LED STATE REGISTER LED DRIVERS LED24
AD0....AD2
LED ADDRESS DECODER
MRST
RESET LAMP TEST LOGIC TEST CONTROL LOGIC
DOUT
TEST DR-00594
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SA8803 PIN DESCRIPTION Pin Designation 1..3 AD0..AD2 Description Device address input pins. The binary code set up on these pins, must match the address field of the control word, before device access may be achieved. These Schmitt-triggered inputs have on-chip pull-up resistors. This output is used for the manufacturers test requirements and MUST be left open. Constant Current Drain Select.This Schmitt-triggered input has on-chip pullup provided. High current LED drive terminal outputs.
4 5 7..10, 12..14, 16..18, 20..21, 24..26 28..30 32..34, 36..38 22 39
DOUT CC
LED1..LED4, LED5..LED7 LED8..LED10, LED11..LED12, LED13..LED15, LED16..LED18, LED19..LED21, LED22..LED24 INTENS This analog input is used to set the drive current supplied to the LED's. A resistor is connected from this pin to VEE. TEST Active low input that enables the internal LED status word to be output from the DOUT pin. This Schmitt-triggered input has on-chip pullup provided. Internally Unconnected. External clock Schmitt-triggered input runs at 8X the data rate (Baud rate). This active low Schmitt-Trigger input may be used to reset all internal registers. When active (low) this input will cause all LED's to be driven for the duration of MRST (lamp test). When MRST goes inactive all LED's will be turned off. On-chip pullup provided. 0V Supply Input for logic (0V) Serial data input. Accept data in the form of an 11-bit information word. This Schmitt-triggered input has onchip pullup provided. Negative Supply Inputs (-5V) Positive Supply Inputs (+5V)
40 41 42
NC CLK MRST
43 44
GND DATA
11, 19, 27, 35 6, 15, 23, 31 Note:
VEE VDD
All inputs and outputs are CMOS compatible, unless otherwise specified. sames
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SA8803 FUNCTIONAL DESCRIPTION 1. Control Word The control word written serially into the DATA pin, will contain 9 information bits. The data structure is illustrated in Figure 2 below. Because the chip address is 3 bits wide, a single chip controller will be able to address 8 SA8803 devices. Each SA8803 can drive 24 LED's, which means that the controller is capable of addressing 192 LED's. The address bits in the control word are internally compared with the address on the AD0..AD2 address lines to determine if the SA8803 is being addressed. Table 1. LED Addresses L5 L4 0 0 0 0 0 0 1 1 1 1 1 1 L3 0 0 0 etc 0 0 1 L2 0 0 1 0 0 1 L1 0 1 0 0 1 1 LED IGNORED 1 2 24 IGNORED
FIGURE 2: CONTROL WORD STRUCTURE 9-BIT CONTROL WORD
SB SB L1 ... L5 A0 ... A2 E S
DR-00595
L1 = = = = =
L2
L3
L4
L5
S
A0
A1
A2
E
SB
START BIT LED BIT ADDRESS INSIDE BANK DEVICE BIT ADDRESS END BIT STATUS BIT
As can be seen from the structure of the control word, the controller should send 1 start bit, 9 data bits, and 1 stop bit. When a LED is addressed its state will be set according to the status bit. A logic one will enable the LED, and a logic zero will disable the LED.
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SA8803 3. LED Intensity Control The LED "on" current (ID ), is determined by the current flowing from the INTENS pin through the external resistor. The values of ID can be calculated as follows: ID = KT. VX R KT - Current Transfer Ratio of the Internal Current Mirror (typically 10.0) R - The programming resistor value VX - The voltage drop across the external resistor (internally controlled to 5.0V) Constant Current Mode When the CC pin is pulled high, the device will draw a constant current from the VDD supply which is equal to all LED's in the "on"condition regardless of the status of the LED's. Clock Characteristics SCLK is the internal synchronous clock derived from the asynchronous external clock applied at the CLK input pin. It divides the external clock by 8. Theoretically the rising edge of SCLK (synchronous Clock) should be in the middle of every bit, as shown in Figure 4. Because of phase shift due to the clock frequency being more or less than 8 times the baud rate, this edge may shift its position with regard to the bit period (BP). The extreme case that may still be tolerated is an edge arriving at either the beginning, or end of bit 11. This represents the maximum shift that can be tolerated for valid data to be received for an inaccurate input clock frequency (FO).
4.
5.
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SA8803 FIGURE 3: TIMING DIAGRAM
BP S DATA BIT 11
S CLK
CLK
1 T0
2
3
4
5 F 0 = 8 x S CLK
6
7
8
DR-00596
The acceptable Clock pulse Period (TO) may be calculated as follows: The rising edge may not shift more than half a bit period (BP), therefore: 11 x BP - (1/2 x BP) <11 x 8 x TO < 11 x BP (1/2 x BP) Therefore: 11 x 8 x TO = 11 x BP (1/2 x BP) (B / 8) .*. TO = (BP / 8) P 22 .*. TO = (BP / 8) 4,55%
The acceptable frequency for the clock FO is calculated as follows: FO = .*. FO = 1 TO
1 (BP / 8) (1 1 ) 22 1 (BP / 8)
But because: BR x 8 = where BR = Baud Rate 22 (1 22) FO = BR x 8 4.55% FO = (BR x 8) x .*.
The SA8803 has been specified for an external clock frequency of 8 times the Baud Rate 3%.
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SA8803 6. Test feature If the TEST pin is pulled low, the status of all 24 LED's are output at pin DOUT in 3 groups of 8 status bits each, with a start bit and a stop bit added. The data rate of this status word is equal to the input data rate (i.e. CLK) devided by 8. The three data word that are serially output at DOUT each contain 11-bit. This means that bit 10 is not used in each case. The words therefore contain a start bit, 8 LED status bits (1 for off, 0 for on). 1 unused bit, and a stop bit. The three groups are output consecutively in the following order: first LED's 1 to 8, then 9 to 16, and then 17 to 24.
ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Supply Voltage, VEE Input or Output Voltage DC Forward Bias Current, Input or Output Storage Temperature (Plastic) Operating Temperature
-0.30 V to +5.50 V 0.30 V to -5.50 V -0.30 V to (VDD +0.30) V 10 mA -40 to 125C 0 - 70
Note 1: Referenced to GND. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect the device reliability. ELECTRICAL CHARACTERISTICS DC Electrical Characteristics Across Temperature Range (Note 1) Symbol Parameter Condition Min Typ Max Unit 0.8 2.0 IOL 4mA IOH 4 mA 2.4 0.1 4.5 0.4 V V V V
TTL INTERFACE V IL Low Level Input Voltage V IH High Level Input Voltage V OL Low Level Ouput Voltage V OH High Level Output Voltage
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SA8803 Symbol Parameter Condition Min Typ Max Unit 1.5 3.5 IO 4 mA IO 4 mA VDD -1.0 3.4 1.4 2.0 4.0 1.0 V V V V V V
CMOS INTERFACE Low Level V IL Input Voltage V IH High Level Input Voltage V OL Low Level Output Voltage V OH High Level Output Voltage VT+ Schmitt. Trig. +ve Threshold VTSchmitt. Trig. -ve Threshold GENERAL IIL Low Level Input Current IIH High Level Input Current IILU Input Current with Pull Up IIHD Input Current with Pull Down IOZ Tri-state Output Leakage V ESD Electrostatic Protection VDD Logic Supply Voltage V SS Analog Supply Voltage KT Current Transfer Ratio KT Delta Current Transfer Ratio ID LED Current FO Operating Frequency 1
V I = VSS VI = VDD V I = VSS VI = VDD VO = OV or VDD C = 100pF R = 1.5Kohm
-10 -10 -200 10 -10 2000 4.5 -5.5
<1 <1 -50 50 <1
10 10 -10 200 10
A A A A A V
5.0 -5.0 10.5
5.5 -4.5
V V
ID = 10 mA Programmed Value Must be 3% of 8 x Baud Rate
15 10 0.4 128 448
% mA kHz
NOTE 1) The operating frequency range for FO is wide enough to cover baud rates from 50 to 56000 bps.
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SA8803 NOTES:
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SA8803
Disclaimer: The information contained in this document is confidential and proprietary to South African MicroElectronic Systems (Pty) Ltd ("SAMES) and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer.
South African Micro-Electronic Systems (Pty) Ltd P O Box 15888, 33 Eland Street, Lynn East, Koedoespoort Industrial Area, 0039 Pretoria, Republic of South Africa, Republic of South Africa
Tel: Fax:
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012 333-6021 012 333-8071 sames
Tel: Fax:
Int +27 12 333-6021 Int +27 12 333-8071

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